DocumentCode
2224033
Title
Design issues of deep submicron wave pipelining technology
Author
Lan, Chen ; Zhimin, Tang
Author_Institution
Inst. of Comput. Technol., Acad. Sinica, Beijing, China
fYear
2001
fDate
2001
Firstpage
62
Lastpage
66
Abstract
This paper introduces strategies for developing wave pipelined systems with deep submicron manufacture technology. The delay model for interconnect wire under deep submicron technology is discussed in detail. With data transport path balancing and routing strategies introduced in this paper, the clock-rate of a wave pipelined circuit can achieve a speedup of 3 to 6
Keywords
VLSI; circuit CAD; circuit layout CAD; delay estimation; digital integrated circuits; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; network routing; pipeline processing; clock-rate speedup; data transport path balancing; deep submicron technology; delay model; interconnect wire; routing strategies; wave pipelined systems; Clocks; Delay effects; Integrated circuit interconnections; Manufacturing; Pipeline processing; Propagation delay; Registers; Routing; Synchronization; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location
Shanghai
Print_ISBN
0-7803-6677-8
Type
conf
DOI
10.1109/ICASIC.2001.982499
Filename
982499
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