DocumentCode
2224035
Title
Hierarchical watermarking in IC design
Author
Charbon, Edoardo
Author_Institution
Cadence Design Syst. Inc., San Jose, CA, USA
fYear
1998
fDate
11-14 May 1998
Firstpage
295
Lastpage
298
Abstract
A formalization of the watermarking problem is presented and basic algorithms for its generation and detection at several abstraction levels are proposed. The concepts of robustness against forgery and theft tracing are analyzed in light of the proposed algorithms
Keywords
industrial property; integrated circuit design; redundancy; topology; IC design; IP protection; abstraction levels; forgery; hierarchical watermarking; robustness; theft tracing; Algorithm design and analysis; Counterfeiting; Electronics industry; Forgery; Industrial electronics; Phase detection; Protection; Robustness; Topology; Watermarking;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location
Santa Clara, CA
Print_ISBN
0-7803-4292-5
Type
conf
DOI
10.1109/CICC.1998.694985
Filename
694985
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