Context reorder buffer: an architectural support for real-time processing on RISC architectures

In this article the authors present a hardware solution to the problem of precise interrupts and exceptions in superscalar RISC CPU architectures. This solution, called context reorder buffer (abbreviated as CRB), is based both on the reorder buffer architecture presented by Smith and Pleszkun in (1988), and on the concept of context, whose application to interrupt processing is an original idea of this work. The CRB architecture assures precise nested interrupts and exceptions, minimal interrupt fetching latency and high throughput. Moreover, our architecture supports speculative execution of depth limited only by the number of entries within the CRB and does not require a change to the current programming model of RISC and real-time CPUs