• DocumentCode
    2224183
  • Title

    Using a hardware model checker to verify software

  • Author

    Edwards, Stephen A. ; Ma, Tony ; Damiano, Robert

  • Author_Institution
    Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    85
  • Lastpage
    90
  • Abstract
    A variety of new algorithms has begun to enable model checking of industrial-sized netlists. This work attempts to apply that technology to the verification of embedded software: C programs that manipulate integers and contain unstructured control flow, but are not recursive and do not dynamically allocate memory. We describe a synthesis procedure for translating a subset of C into a netlist and present experiments that show the models it builds seem to be harder to verify than typical hardware circuits, suggesting the problem has a different character. Although we only have preliminary experimental results, they help to identify the challenges inherent in verifying this class of software and leave open the possibility of more successful approaches
  • Keywords
    C language; electronic design automation; embedded systems; program verification; C programs; C subset netlist translation procedure; embedded software verification; finite-state model checking; hardware circuits; hardware model checker; industrial-sized netlists; integer manipulation; memory allocation; model checking; nonrecursive programs; software verification; synthesis procedure; unstructured control flow; Arithmetic; Automatic test pattern generation; Circuit synthesis; Circuit testing; Decision making; Embedded software; Hardware; Signal generators; Signal synthesis; Software algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2001. Proceedings. 4th International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    0-7803-6677-8
  • Type

    conf

  • DOI
    10.1109/ICASIC.2001.982504
  • Filename
    982504