CEP: a clock-driven ECO placement algorithm for standard-cell layout

Author

Liu, Yi ; Hong, Xianlong ; Cai, Yici ; Wu, Weimin

Author_Institution

Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China

fYear

2001

fDate

2001

Firstpage

118

Lastpage

121

Abstract

Incremental placement or ECO (engineer change order) placement is a new field in VLSI layout to meet the demand of high performance design. In this paper, a novel clock-driven ECO placement algorithm, CEP, is presented for standard cell layout design. It considers clock skew information in the placement stage, modifies the positions of cells locally to make better preparation for the clock routing. Experimental results show that CEP can improve the skew bounds distribution evidently, with little influence on other performance aspects

Keywords

VLSI; circuit layout CAD; clocks; integrated circuit layout; network routing; timing; CEP clock-driven ECO placement algorithm; ECO placement; VLSI layout; clock routing; clock skew information; clock-driven ECO placement algorithm; engineer change order placement; incremental placement; local cell position modification; placement stage; skew bounds distribution; standard cell layout design; standard-cell layout; Algorithm design and analysis; Binary search trees; Circuits; Clocks; Delay; Flip-flops; Logic; Pins; Routing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982512

Filename

982512