Title :
ASICosyn: co-synthesis of conditional task graphs with custom ASICs
Author :
Xie, Yuan ; Wolf, Wayne
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
Abstract :
This paper describes a co-synthesis system called ASICosyn, which is a cosynthesis tool for distributed real time embedded systems that considers various ASIC implementations for tasks. We use Monet, a behavioral level architectural exploration system from Mentor Graphics, to generate multiple implementations of a behavioral description of an ASIC and to analyze their performance. A mutual exclusive detection algorithm and corresponding allocation and scheduling algorithm are developed for the conditional task graph to take care of the control dependencies in the task graph model
Keywords :
application specific integrated circuits; circuit CAD; embedded systems; hardware-software codesign; integrated circuit design; processor scheduling; software tools; ASIC behavioral description; ASIC implementations; ASICosyn hardware-software co-synthesis tool; Monet behavioral level architectural exploration system; allocation/scheduling algorithm; co-synthesis system; co-synthesis tool; conditional task graphs; control dependencies; custom ASICs; distributed real time embedded systems; multiple ASIC implementations; mutual exclusive detection algorithm; task graph model; Application specific integrated circuits; Computer architecture; Control system synthesis; Costs; Detection algorithms; Embedded system; Graphics; Hardware; Processor scheduling; Real time systems;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982515
