A clustering-based algorithm for zero-skew clock routing with buffer insertion

Clock routing plays an important role in layout design, especially for synchronous circuits. In this paper, a zero-skew clock routing algorithm with fast clustering and improvement methods is proposed. During clock routing tree construction, we introduce a new cell matching strategy to merge two subtrees. Appropriate buffers are selected and inserted into the clock routing tree to reduce path delay and achieve zero-skew. The clustering method has accelerated the algorithm speed significantly, as shown by the experimental results