The design of acquisition circuit for grating digital signal based on FPGA

In order to resolve the poor suppression capability of noise and fitter interference existing in grating encoder high-rate subdivision and the poor accuracy of kam-to, counting circuit, we design a circuit based on FPGA to realize multiplier, kam and filter for the output of two-way orthogonal signal generated by Incremental Optical Encoder. The system is mainly divided into three modules such as filtering, multiplier kam-to and counting. The main function of filter circuit is to eliminate the jitter and noise interference existing in the quadrate encoder signals. Kam-to multiplier circuit can accurately judge the full cycle and half-cycle of incremental encoder, at the same time can make fourfold multiplier. Counting circuit can use IP cores owned by Quartus II which is not restricted on the median. At last, timing simulation based on Modelsim carried on the three modules;the results show that the design method will help improve the controlled object of measurement precision and control accuracy.