A new algorithm for computing the “effective capacitance” in deep sub-micron circuits

In this paper we introduce an algorithm which computes the effective capacitance with improvements in both accuracy and speed over previously published algorithms. Speed improvements are achieved by replacing complex circuit analysis equations used to compute intermediate values of effective capacitance with a characterized table which is a function of circuit parameters. Accuracy improvements are attained by replacing model approximations for the driver cell with a representative SPICE driver model which accounts for higher order effects of deep sub-micron (DSM) circuits. This new algorithm interfaces with industry-standard empirical timing libraries providing an efficient interface with timing driven EDA applications