Low power design of embedded NOR type FLASH memory module (EFMM)

Author

Myung-Ok, Mike Lee ; Lee, Seung-Min ; Kim, Young-Min ; Kim, Young-Cheol

Author_Institution

Dept. of Inf. & Commun. Eng., Dongshin Univ., Chonnam, South Korea

fYear

2001

fDate

2001

Firstpage

216

Lastpage

219

Abstract

A Novel 40-ns high speed (HS) and 30 mA low power (LP) embedded flash memory modules (EFMM) such as 1 M flash memory cell array, three (4V, 5V, 9V) positive high voltage circuits and -7V negative high voltage circuit plus VHDL-modeled logic sub-systems implemented on 0.25 μm CMOS SLP/5LM technology are presented. It is shown that our EFMM which is being used in multi-cube results in 30 mA active read current and 100 μA standby current. Mixed mode design for analogs-high voltage charge pump shows stable 9V high for programming and further 1.2V bandgap reference voltage interfacing with the high voltage circuits and for logic designs are developed by optimized IP-standard (set by Synopsys) VHDL modeling. Chip size with 56-pin indicates 5.7 mm ²

Keywords

CMOS memory circuits; NOR circuits; circuit optimisation; flash memories; hardware description languages; high-speed integrated circuits; integrated circuit design; logic CAD; low-power electronics; -7 V; 0.25 micron; 1 Mbit; 1.2 V; 100 muA; 30 mA; 4 to 9 V; 40 ns; CMOS; EFMM; Synopsys; VHDL-modeled logic sub-systems; active read current; bandgap reference voltage; embedded NOR type flash memory module; high speed circuits; high voltage charge pump; low power design; mixed mode design; multi-cube; optimized IP-standard; positive high voltage circuits; standby current; CMOS logic circuits; CMOS memory circuits; CMOS technology; Charge pumps; Flash memory; Flash memory cells; Log periodic antennas; Logic arrays; Logic programming; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982536

Filename

982536