Timing qualification of a 0.25-μm CMOS ASIC library using BSIM3 FET models

Extensive circuit-level model-to-hardware correlation using BSIM3 FET models is shown for the first time. We demonstrate that the models are capable of achieving error percentages in single digits across a wide range of circuit types and environmental conditions on devices with 0.18-μm nominal L_eff in a 0.25-μm generation CMOS technology. Further, we verify the model can accurately simulate hardware which has intentionally varied L_eff and V_t for the purpose of simulating long term process variation. Additionally, a unique statistical analysis technique for determining model error contributors is presented. Finally, a rigorous new methodology for the timing qualification of an ASIC library is described