Title :
Low power State Machine design on FPGAs
Author :
Saleem, Adil ; Khan, Shoab A.
Author_Institution :
Dept. of Comput. Eng., Nat. Univ. of Sci. & Technol., Rawalpindi, Pakistan
Abstract :
This paper presents an approach to reduce the power consumption of FPGA based digital circuits at FSM design level. The approach is based on clock gating technique. By using control signals at FSM level, we have limited the clock switching and other signals transitions in the system, leading to reduced dynamic power consumption of the systems. Our results have shown up to 7% reduction in dynamic power consumption.
Keywords :
clocks; field programmable gate arrays; finite state machines; integrated circuit design; logic design; low-power electronics; FPGA; FSM design level; clock gating; clock switching; control signal; digital circuit; low power state machine design; reduced dynamic power consumption; Lead; Clock gating; FPGA; FSM; Low power;
Conference_Titel :
Advanced Computer Theory and Engineering (ICACTE), 2010 3rd International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4244-6539-2
DOI :
10.1109/ICACTE.2010.5579416
