An analytical 3-D placement that reserves routing space

This paper presents an analytical model of 3-D VLSI layout and the corresponding placement technique. Based on the analytical model defined in a continuous space for imposing strong convexity, an objective function, and a set of placement constraints including those involving routing space requirements, have been derived. As the placement is optimized by a nonlinear programming technique, the placement topology and the routing space management are considered simultaneously and globally over the entire layout space