Title :
Design of a 11 bit 10Ms/s pipelined A/D converter
Author :
Bailin, Peng ; Jun, Cheng ; Guican, Chen
Author_Institution :
Inst. of Microelectron., Xi´´an Jiaotong Univ., China
Abstract :
A 11 bit 10Ms/s A/D Converter (ADC) is presented. The converter consists of a five-stage pipelined architecture and adopts the negative redundant digital correction technique to correct errors in the gain and offset. The fully differential circuitry is used to improve the power supply rejection and reduce errors resulting from the charge injection. The ADC is designed in a 0.6um CMOS technology and dissipates 50mW with a 3v power supply
Keywords :
CMOS integrated circuits; analogue-digital conversion; pipeline processing; 0.6 micron; 11 bit; 3 V; 50 mW; A/D converter; CMOS technology; charge injection; circuit design; fully-differential circuit; negative redundant digital correction; pipelined architecture; power supply rejection; CMOS technology; Differential amplifiers; Digital systems; Error correction; Feedback circuits; Power supplies; Samarium; Switches; Switching circuits; Voltage;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982561
