Title :
HDL filter for optimized area-delay minimization in FPGA synthesis
Author_Institution :
Ain Shams University
Keywords :
Area measurement; Circuit synthesis; Delay; Field programmable gate arrays; Filtering; Filters; Hardware design languages; Logic; Minimization; Signal synthesis;
Conference_Titel :
Electrical, Electronic and Computer Engineering, 2004. ICEEC '04. 2004 International Conference on
Print_ISBN :
0-7803-8575-6
DOI :
10.1109/ICEEC.2004.1374376
