Title :
An efficient and scalable VLSI implementation of DES
Author :
Liang, Deng ; Hongyi, Chen
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
For the rapid development of Information Technology, data security becomes more and more important. The best way to solve the security problem is to implement ciphers with ASIC. This paper describes an efficient and scalable VLSI implementation of DES algorithm. Various implementing techniques are compared and the most efficient one is chosen. 1.2um CMOS technology is used to implement a testing chip for testing the performance of this design. It can encrypt 40M bits of data per second at 10MHz clock frequency. For some accessorial use, this chip can also be a random number generator (RNG)
Keywords :
CMOS integrated circuits; VLSI; application specific integrated circuits; cryptography; random number generation; 1.2 micron; 10 MHz; 40 Mbit/s; ASIC; CMOS chip; DES algorithm; VLSI; cipher; data security; information technology; random number generator; Application specific integrated circuits; CMOS technology; Clocks; Cryptography; Data security; Frequency; Information security; Information technology; Testing; Very large scale integration;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982570
