DocumentCode :
2225749
Title :
A 1024-bit RSA crypto-coprocessor for smart cards
Author :
Shuguo, Li ; Runde, Zhou ; Yuanqing, Ge
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
fYear :
2001
fDate :
2001
Firstpage :
352
Lastpage :
355
Abstract :
We propose a new VLSI architecture for high-radix modular multiplier to compute RSA public-key cryptosystem based on the modified Montgomery algorithm. A 1024-bit RSA crypto-coprocessor has been implemented based our proposed VLSI architecture. The proposed architecture is performed in a pipelined fashion and takes about u+6√u- clock cycles to compute one u-bit modular multiplication and about 1.5u(u+6√u) clock cycles to calculate u-bit modular exponentiation. The simulation shows that gate count of the processor is about 38K, and the time to calculate 1024-bit modular exponentiation is about 374ms at 5MHz. Compared with previous methods, our proposed architecture can achieve good performance in chip area and speed for smart cards
Keywords :
VLSI; coprocessors; pipeline arithmetic; public key cryptography; smart cards; 1024 bit; 5 MHz; RSA crypto-coprocessor; VLSI chip; high-radix Montgomery algorithm; modular exponentiation; modular multiplication; pipeline architecture; public key cryptography; smart card; Authentication; Clocks; Computational modeling; Computer architecture; Data security; Digital signatures; Microelectronics; Public key cryptography; Smart cards; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
Type :
conf
DOI :
10.1109/ICASIC.2001.982573
Filename :
982573
Link To Document :
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