Title :
Pulse mode multilayer neural network based on floating point number representation
Author_Institution :
Dept. of Comput. Sci. & Intelligent Syst., Oita Univ., Japan
Abstract :
This paper proposes a new type of pulse mode multilayer neural network (MNN) that uses floating point number system for synapse weight value. Combined with pulse mode operation, the floating point operation is implemented without a multiplier. The proposed neuron, synapse multiplier and experimental MNN are implemented on field programmable gate arrays (FPGA) and various experiments are conducted to test the feasibility of the system. These experiments prove that the proposed MNN architecture can be used for applications which require high precision in their calculation
Keywords :
field programmable gate arrays; floating point arithmetic; neural chips; neural net architecture; FPGA implementation; digital ANN architecture; field programmable gate arrays; floating point number representation; neuron; pulse mode multilayer neural network; synapse multiplier; synapse weight value; Application software; Computer architecture; Computer science; Field programmable gate arrays; Frequency conversion; Intelligent systems; Multi-layer neural network; Neural network hardware; Neural networks; Neurons;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.856017