DocumentCode
2225908
Title
Design and implementation of HDTV PES encoder
Author
Feng, Wang ; Wenjun, Zhang ; Wei, Ye
Author_Institution
Inst. of Image Commun. & Inf. Process., Shanghai Jiaotong Univ., China
fYear
2001
fDate
2001
Firstpage
382
Lastpage
385
Abstract
The hardware design of HDTV PES encoder is given in this paper. The encoder builds up a HDTV PES stream by six SDTV ES streams with different bitrate. Coded data is reorganized to form a new PES stream; meanwhile coding parameters are modified. The PES stream is output in stable bitrate. All these functions are implemented in one CPLD. Experimental results show that the decoded image is improved, and constant bitrate can be maintained at the same time
Keywords
high definition television; programmable logic devices; video coding; CPLD; HDTV; PES encoder; SDTV ES streams; bitrate; coding parameters; hardware design; Application specific integrated circuits; Bit rate; Decoding; Equations; HDTV; Hardware; Image communication; Information processing; Prototypes; Streaming media;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location
Shanghai
Print_ISBN
0-7803-6677-8
Type
conf
DOI
10.1109/ICASIC.2001.982580
Filename
982580
Link To Document