Parasitic and mismatch modeling for optimal stack generation [in CMOS]

Control of parasitic capacitance and minimization of layout mismatch are very crucial in the analog physical design automation. In this paper we study the techniques for modeling the distributed parasitic capacitance, modeling the parasitic parameter mismatch due to process gradient and modeling the inner stack routing mismatch. Based on the proposed models, a transistor folding technique and a dummy transistor insertion technique are developed to optimize the stack shape, control of parasitics and guarantee the generation of an Eulerian graph for a given diffusion graph