DocumentCode
2226132
Title
Design of constant-coefficient multipliers
Author
Chen, Dingjun ; Aoki, Takafumi ; Homma, Naofumi ; Higuchi, Tatsuo
Author_Institution
Higuchi Lab., Tohoku Univ., SendaiFliguchi Lab, Japan
fYear
2001
fDate
2001
Firstpage
416
Lastpage
419
Abstract
This paper examines a conventional method for optimizing the design of CSD multipliers based on parallel Signed-Weight (SW) counter-tree architecture and another novel evolutionary-computation approach to automatically seeking optimal designs of multipliers. The comparisons of experimental results between them indicate that the evolutionary-computation method in most cases is comparable to or outperforms the conventional designs using CSD number representation
Keywords
circuit optimisation; digital arithmetic; evolutionary computation; multiplying circuits; parallel architectures; trees (mathematics); CSD number representation; constant-coefficient multiplier; design optimization; evolutionary computation; parallel signed-weight counter-tree architecture; Arithmetic; Concurrent computing; Counting circuits; Delay; Design optimization; Digital signal processing; Digital systems; Encoding; Hardware; Parallel processing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location
Shanghai
Print_ISBN
0-7803-6677-8
Type
conf
DOI
10.1109/ICASIC.2001.982589
Filename
982589
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