Title :
Design of a high performance Reed-Solomon decoder with switch box control logic [HDTV]
Author :
Hai-kun, Zhu ; Bo, Shen ; Qian-ling, Zhang
Author_Institution :
ASIC & Syst. State-Key Lab., Fudan Univ., Shanghai, China
Abstract :
In this paper, a pipeline Reed-Solomon decoder based on time domain decoding technique is presented. High throughput is achieved by parallel computation in the modified Euclid algorithm block, and the complex control circuit is simplified by a switch box strategy. In addition, the constant finite field multiplier is optimized to reduce the chip area, thus making the decoder suitable for HDTV
Keywords :
Reed-Solomon codes; decoding; high definition television; multiplying circuits; pipeline processing; time-domain analysis; HDTV; Reed-Solomon decoder; chip area; constant finite field multiplier; modified Euclid algorithm block; parallel computation; pipeline decoder; switch box control logic; throughput; time domain decoding technique; Circuits; Computer architecture; Concurrent computing; Decoding; Error correction codes; Galois fields; Logic design; Polynomials; Reed-Solomon codes; Switches;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982598
