Title :
A 3.3 V analog adaptive line-equalizer for fast Ethernet data communication
Author :
Babanezhad, Joseph N.
Author_Institution :
Plato Labs., San Jose, CA, USA
Abstract :
An adaptive line-equalizer has been developed for 100 Mb/sec Fast Ethernet data communication. For a 100 m CAT3 UTP cable the output jitter is 2 nsec while for that of a 125 m CAT5 UTP cable it is 2.8 nsec. The device is fabricated in 0.4 μ digital CMOS process where it consumes 65 mW from a 3.3 V power supply
Keywords :
CMOS digital integrated circuits; adaptive equalisers; data communication equipment; intersymbol interference; jitter; local area networks; 0.4 mum; 100 Mbit/s; 125 m; 3.3 V; 65 mW; CAT3 UTP cable; Ethernet data communication; analog adaptive line-equalizer; digital CMOS; high speed data communication; output jitter; Adaptive equalizers; Circuits; Communication cables; Data communication; Ethernet networks; Filtering; Filters; Resistors; Servomechanisms; Transconductance;
Conference_Titel :
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-4292-5
DOI :
10.1109/CICC.1998.694995
