An advanced VLSI architecture of RS decoders for advanced TV

The Reed-Solomon (RS) decoders which are designed for advanced TV (ATV) are reported. The architecture has three features. First, it uses a bit clock as an operating clock rather than a symbol clock. Second, the recursive Berlekamp algorithm (RBA) is adopted to calculate an error locator polynomial. The combination of bit clock and RBA reduces the number of gates used for implementation dramatically. Finally, a shifter structure is suggested in order to solve the routing area problem which might be caused incidentally in recursive architectures. The ideas are modified and applied to RS decoders for ATV