Efficient design of application specific DSP cores using FPGAs

Author

Attri, Sanjay ; Sohi, B.S. ; Chopra, Y.C.

Author_Institution

Electron. & Commun. Eng.Dept, Tech. Teachers´´ Training Inst., Chandigarh, India

fYear

2001

fDate

2001

Firstpage

462

Lastpage

466

Abstract

This paper focuses on design of digital signal processing (DSP) cores for compact and efficient implementations of real time DSP applications on field programmable gate arrays (FPGAs) using distributed arithmetic. The resulting serial distributed arithmetic (SDA) and the parallel-distributed arithmetic (PDA) designs are implemented. As an example, the implementation of a 16-tap 8-bit Finite impulse response (FIR) filter on a Xilinx XC4000E FPGA using SDA and PDA techniques has been examined. An analysis of the performance comparison is described. The results show that PDA designs with a digit size of 2 bits are more efficient in area-time product parameter than those of SDA implementations

Keywords

FIR filters; application specific integrated circuits; digital signal processing chips; distributed arithmetic; field programmable gate arrays; integrated circuit design; 8 bit; FIR filter; FPGA; Xilinx XC4000E; application specific DSP core; area-time product; design; parallel distributed arithmetic; serial distributed arithmetic; Arithmetic; Circuits; Consumer electronics; Digital signal processing; Educational institutions; Electronic mail; Field programmable gate arrays; Finite impulse response filter; Signal processing; Time to market;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982600

Filename

982600