Controller redesign based clock and register power minimization

Clock gating is an effective technique for minimizing dynamic power in sequential circuits. However, clock gating has some practical difficulties viz., possibility of glitches on the gated clock and in use of static timing analysis for verifying timing of the design. In this paper we describe a robust scheme for power minimization that eliminates these difficulties of clock gating and yet provides nearly the same power savings. This scheme does not rely on propagation delays in the circuit for functioning, and is robust across process technologies. In this scheme, the controllers sequencing operations in a datapath are modified so that the control signals themselves are used as clocks for registers in the datapath. Since these “control clocks” typically operate at lower frequencies, power is saved in the registers and in the clock drivers. This scheme also preserves the cycle boundaries on which registers in the original circuit load data, thereby allowing reuse of test cases developed for the functional verification of the original circuit