On the utilization of strength-reduced architectures for adaptive equalizers

Traditionally adaptive equalizers for complex signals were built using a cross-coupled architecture. Strength-reduction is a technique than can be employed to trade-off power expensive multipliers, with adders. However, predicted power savings given so far are based on simplified estimates that can hardly fit a general case. This paper attempts to achieve more realistic power estimates based on actual implementation considerations and actual operating conditions. A 256-QAM decision-feedback equalizer (DFE) with 5 complex taps was taken as a case study. Simulation results indicate that the achieved savings could be channel dependent depending on the utilized multipliers