Architectural adaptation for power and performance

Author

Tang, Weiyu ; Veidenbaum, Alexander V. ; Gupta, Rajesh

Author_Institution

Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA

fYear

2001

fDate

2001

Firstpage

530

Lastpage

534

Abstract

Architectural adaptation provides an attractive means to ensure high performance and low power. Adaptable architectural components support multiple mechanisms that can be tailored to application needs. In this paper, we show the benefits of architectural adaptation for power and performance using the cache memory as an example. Dynamic L0 cache management selects either L0 cache or L1 cache for instruction fetch. It reduces average power consumption in the instruction cache by 29.5% with only 0.7% performance degradation. Dynamic fetch size profiling changes cache fetch size at run-time to improve locality utilization. It improves average benchmark performance by 15%

Keywords

cache storage; instruction sets; low-power electronics; memory architecture; reconfigurable architectures; storage management chips; Ll cache; adaptable architectural components; application-specific customization; architectural adaptation; average power consumption; benchmark performance; cache fetch size; cache memory; dynamic L0 cache management; dynamic fetch size profiling; high performance; instruction cache; instruction fetch; locality utilization; low power; multiple mechanisms; Application software; Cache memory; Computer architecture; Computer science; Degradation; Energy consumption; Hardware; Multiprocessor interconnection networks; Power system management; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982617

Filename

982617