A CMOS reduced-area SRAM cell

Author

Joubert, T.-H. ; Seevinck, E. ; du Plessis, M.

Author_Institution

Dept. of Electron. & Electron. Eng., Pretoria Univ., South Africa

Volume

3

fYear

2000

fDate

2000

Firstpage

335

Abstract

In CMOS, an SRAM cell containing six transistors and five routing wires is generally used. If a smaller number of transistors and/or fewer connection lines were possible, the packing density of SRAM chips may be improved. In this paper, a four-transistor SRAM cell for implementation in a standard digital CMOS process is proposed. The implementation of the smallest area cell in a 1.2 μm n-well CMOS process shows successful cell operation. Two memory block architectures are also discussed, as well as the specific cell configurations for correct operation. Depending on the memory block architecture, the four-transistor cell area reduction, when compared to a six-transistor cell, is either 14.7% or 37.3%

Keywords

CMOS memory circuits; SRAM chips; integrated circuit layout; memory architecture; 1.2 micron; CMOS SRAM cell; SRAM chips; four-transistor SRAM cell; memory block architectures; memory cell area reduction; n-well CMOS process; packing density improvement; reduced-area SRAM cell; standard digital CMOS process; CMOS process; CMOS technology; Inverters; MOSFETs; Monitoring; Random access memory; Thin film devices; Threshold voltage; Transistors; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856065

Filename

856065