DocumentCode :
2227160
Title :
High-speed, low-complexity fir filter using multiplier block reduction and polyphase decomposition
Author :
Martinez-Peiro, Marcos ; Wanhammar, Lars
Author_Institution :
Tech. Univ. of Valencia
Volume :
3
fYear :
2000
fDate :
2000
Firstpage :
367
Lastpage :
370
Keywords :
Adders; Arithmetic; CMOS process; Costs; Digital filters; Electronic mail; Energy consumption; Finite impulse response filter; IIR filters; Interpolation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Print_ISBN :
0-7803-5482-6
Type :
conf
DOI :
10.1109/ISCAS.2000.856073
Filename :
856073
Link To Document :
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