VHDL modeling and analysis of error-control specific circuits for multiple-modular redundant systems with concurrent error location capability

Multiple-modular redundancy has found many applications in fault-tolerant systems with high reliability and safety requirements. Concurrent error detection or correction circuits and fail-safe I/O circuits (such as decoders, comparators, and voters) named as error-control specific circuits (ECSCs) play very important roles in these fault-tolerant systems and other highly available commercial systems. Recently, they are used in some ASICs design. In high level synthesis and ASIC design, these ECSCs can be provided in the types of standard or semi-custom cells. This paper presents several new VHDL models of ECSCs for hardware redundant systems with the capability of concurrent error location. All models proposed are verified by simulation using Active-VHDL. The hardware complexity and propagation delays of these models are given