Title :
High-speed reduced-state sequence estimation
Author :
Haratsch, Erich F. ; Azadet, Kamran
Author_Institution :
DSP & VLSI Syst. Res., Lucent Technol. Bell Labs., Holmdel, NJ, USA
Abstract :
Reduced-state sequence estimation (RSSE) is a suboptimal modification of the Viterbi algorithm (VA) which reduces the computational complexity of maximum likelihood sequence estimation. However, the maximum achievable throughput of RSSE may be significantly lower than the VA, as in addition to the add-compare-select function the critical path comprises branch metric computation, survivor memory operations, and decision-feedback calculation, This paper shows that precomputation of branch metrics can shorten the critical path of RSSE such that its delay becomes of the same order as the VA
Keywords :
AWGN; Viterbi detection; automatic repeat request; computational complexity; intersymbol interference; maximum likelihood sequence estimation; Viterbi algorithm; add-compare-select function; branch metric computation; branch metrics; computational complexity; decision-feedback calculation; delay; maximum achievable throughput; maximum likelihood sequence estimation; reduced-state sequence estimation; suboptimal modification; survivor memory operations; AWGN; Computational complexity; Decoding; Delay estimation; Intersymbol interference; Maximum likelihood estimation; Modulation coding; Samarium; Throughput; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.856078