DocumentCode
2227296
Title
A high speed 0.25 μm 64-bit CMOS adder design
Author
Xu-guang, Sun ; Zhi-Gang, Mao ; Feng-chang, Lai ; Yi-zheng, Ye
Author_Institution
Microelectron. Center, Harbin Inst. of Technol., China
fYear
2001
fDate
2001
Firstpage
581
Lastpage
583
Abstract
A fast 64-bit dynamic adder has been designed for high performance microprocessors in 2.5-V 0.25-μm 1-poly 5-metal CMOS technology. Fast carry signals can only be obtained by fast G (Generation) and P (Propagation) terms. Integrating dynamic CMOS logic, the Kogge & Stone algorithm and a new circuit architecture, the adder comprises 7 k FETs and has 660 ps addition latency under nominal conditions
Keywords
CMOS logic circuits; adders; carry logic; high-speed integrated circuits; integrated circuit design; low-power electronics; 0.25 micron; 1-poly 5-metal CMOS technology; 2.5 V; 64 bit; 64-bit dynamic adder; 660 ps; Kogge Stone algorithm; addition latency; addition time; circuit architecture; dynamic CMOS logic; fast carry signals; fast generation terms; fast propagation terms; high performance microprocessor; high speed 64-bit CMOS adder design; Added delay; Adders; Algorithm design and analysis; CMOS logic circuits; CMOS technology; Circuit synthesis; Computer architecture; Equations; Microprocessors; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location
Shanghai
Print_ISBN
0-7803-6677-8
Type
conf
DOI
10.1109/ICASIC.2001.982630
Filename
982630
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