Title :
On accelerating slicing floorplan design with boundary constraints
Author :
Liu, En-Cheng ; Lin, Tu-Hsing ; Wang, Rng-Chi
Author_Institution :
Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
Abstract :
Recently Young and Wong extended the well-known simulated annealing based Wong-Liu algorithm [1986] to solve the problem of slicing floorplan design with boundary constraints. The main idea behind the Young-Wong algorithm [1999] is to determine the boundary information of each module in a floorplan by traversing the corresponding normalized Polish expression from right to left once. By carefully examining each of the three types of moves adopted by the Young-Wong algorithm for generating a new normalized Polish expression, we observe that it is very likely that only a subset of modules might have the boundary information changed in the new normalized Polish expression, and hence only the boundary information for those modules needs to be recomputed. Based on the observation, we improve the Young-Wong algorithm by providing methods to accelerate the boundary information computation
Keywords :
circuit layout CAD; integrated circuit interconnections; integrated circuit layout; modules; simulated annealing; Wong-Liu algorithm; Young-Wong algorithm; boundary constraints; boundary information computation; normalized Polish expression; simulated annealing; slicing floorplan design; Acceleration; Algorithm design and analysis; Computational modeling; Computer simulation; Constraint theory; Costs; Design engineering; Shape; Simulated annealing;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.856081