Title :
Speed and resource issues on algorithm design and implementation with hardware
Author :
Zibin, Dai ; Shunxin, Zhang
Author_Institution :
PLA Inf. Eng. Univ., Zhengzhou, China
Abstract :
Speed and resource issues on algorithm design and implementation with hardware are discussed in this paper. Two approaches to improve system-processing speed and to save logic resource have been proposed. Furthermore, quantitative analysis is performed on the results
Keywords :
field programmable gate arrays; high-speed integrated circuits; logic CAD; pipeline processing; programmable logic devices; 6-input-4-output logic function; CPLD/FPGA; FLEX series CPLD; algorithm design; hardware implementation; logic resource; pipelining algorithm structure; quantitative analysis; resource issues; speed issues; system-processing speed; Algorithm design and analysis; Circuit synthesis; Clocks; Computer aided software engineering; Delay; Hardware; Logic circuits; Logic design; Logic devices; Logic functions;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982632
