DocumentCode
2227377
Title
Speed and resource issues on algorithm design and implementation with hardware
Author
Zibin, Dai ; Shunxin, Zhang
Author_Institution
PLA Inf. Eng. Univ., Zhengzhou, China
fYear
2001
fDate
2001
Firstpage
588
Lastpage
591
Abstract
Speed and resource issues on algorithm design and implementation with hardware are discussed in this paper. Two approaches to improve system-processing speed and to save logic resource have been proposed. Furthermore, quantitative analysis is performed on the results
Keywords
field programmable gate arrays; high-speed integrated circuits; logic CAD; pipeline processing; programmable logic devices; 6-input-4-output logic function; CPLD/FPGA; FLEX series CPLD; algorithm design; hardware implementation; logic resource; pipelining algorithm structure; quantitative analysis; resource issues; speed issues; system-processing speed; Algorithm design and analysis; Circuit synthesis; Clocks; Computer aided software engineering; Delay; Hardware; Logic circuits; Logic design; Logic devices; Logic functions;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location
Shanghai
Print_ISBN
0-7803-6677-8
Type
conf
DOI
10.1109/ICASIC.2001.982632
Filename
982632
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