Scan test in 18×18 bits Booth coding-Wallace tree multiplier

Author

Dong-Hui, Wang ; Jie, Rum ; Yungang, Li ; Chaohuan, Hou

Author_Institution

Inst. of Semicond., Acad. Sinica, Beijing, China

fYear

2001

fDate

2001

Firstpage

624

Lastpage

627

Abstract

Scan test can be inserted around hard IP cores that have not been designed with DFT approaches. An 18×18 bits Booth coding-Wallace tree multiplier has been designed with full custom approach with 0.6 μm CMOS technology. When we reuse the multiplier in another chip, scan chain has been inserted around it to increase the fault coverage. After scan insertion, the multiplier needs 4.7% more area and 24.4% more delay time, while the fault coverage reaches 95%

Keywords

CMOS logic circuits; application specific integrated circuits; boundary scan testing; delays; design for testability; fault diagnosis; industrial property; integrated circuit testing; multiplying circuits; trees (mathematics); 0.6 micron; 18 bit; Booth coding-Wallace tree multiplier; CMOS technology; DFT; area; delay time; fault coverage; full custom approach; hard IP cores; scan insertion; scan test; Acoustic testing; Adders; Built-in self-test; CMOS technology; Chaos; Circuit faults; Design for testability; Digital signal processing chips; Discrete Fourier transforms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982641

Filename

982641