Acquisition-time minimization and merged-capacitor switching techniques for sampling-rate and resolution improvement of CMOS ADCs

This paper describes acquisition-time minimization and merged-capacitor switching (MCS) techniques which improve the signal processing speed and resolution of CMOS analog-to-digital converters (ADCs). The proposed acquisition-time minimization technique, which is demonstrated with a 12 b 50 MHz ADC prototype, is accomplished by controlling the transconductance of a two-stage amplifier and the proposed MCS technique improves sampling rate by reducing the number of capacitors used in conventional ADCs. The capacitor mismatch can be minimized without additional power consumption, die area, and the loss of sampling rate, when the size of each unit capacitor is increased as much as the number of capacitors reduced by the MCS technique. The ADC resolution based on the proposed MCS technique is extended further by employing a conventional commutated feedback capacitor switching (CFCS) technique