A new self-test structure for at-speed test of crosstalk in SoC busses

Author

Yang, Jun ; Hu, Chen ; Youhua Shi ; Zhang, Zhe ; Shi, Youhua

Author_Institution

Nat. ASIC Syst. Eng. Center, Southeast Univ., Nanjing, China

fYear

2001

fDate

2001

Firstpage

633

Lastpage

636

Abstract

The use of deep submicron process technologies increases the probability of crosstalk faults in the bus of a system-on-a-chip (SoC). Though a self-testing methodology based on MA fault model has been developed, its area overhead of test logic is excessive. This paper proposed a new error detector (ED) and new test patterns whose overhead is decreased down to only approximately 50% of the old methodology on average. A behavior fault simulation is used to validate the self-testing structure described

Keywords

VLSI; application specific integrated circuits; automatic test pattern generation; built-in self test; circuit simulation; crosstalk; error detection; fault simulation; integrated circuit testing; SoC busses; area overhead; at-speed test; behavior fault simulation; crosstalk; deep submicron process technologies; error detector; overhead; self-test structure; test patterns; Automatic testing; Built-in self-test; Capacitance; Circuit faults; Crosstalk; Delay effects; Inductance; Integrated circuit interconnections; Logic testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982643

Filename

982643