A novel reliable routing algorithm for network on chips

As technology scales, fault tolerance is becoming a key concern in on-chip communication. In this paper we present a methodology to design fault-tolerant routing algorithms for regular direct interconnection networks. It supports fully adaptive routing, does not degrade performance in the absence of faults, and supports a reasonably large number of faults without significantly degrading performance. Consequently, this work examines fault tolerant communication algorithms for use in the NoC domain. Before two different flooding algorithms, a random walk algorithm and an Intermediate Node Algorithm have been investigated. The first three algorithms have an exceedingly high communication overhead and cause huge congestion in usual traffics. The fourth is a static fault model which focuses on the faults knowing in advance where they are located. We have developed a new dynamic algorithm based on intermediate node concept and stress value concept to overcome all of mentioned constraints.