Module recognition and its application to LVS of ASIC

Author

Lin-chu, Shi

Author_Institution

China Huajing Electron. Group Corp., Jiangsu, China

fYear

2001

fDate

2001

Firstpage

693

Lastpage

695

Abstract

LVS (Layout Versus Schematic) is an important procedure in ASIC design. LVS includes 2 steps: extraction of devices and net-lists from layout with an EDA system to form the schematic, the so-called "extracted schematic", and identification and verification of the extracted schematic with another schematic designed independently upon layout. The former is more important than the latter. Module recognition plays a very effective role during extraction of schematic from layout. The theoretical principle is described in the paper, followed by a detailed description of an actual method, with some examples of bipolar analog ASIC design

Keywords

analogue integrated circuits; application specific integrated circuits; bipolar analogue integrated circuits; circuit layout CAD; integrated circuit layout; ASIC design; EDA system; LVS; bipolar analog ASIC; extracted schematic; layout versus schematic; module recognition; Application specific integrated circuits; Bipolar transistor circuits; Circuit synthesis; Contacts; Electronic design automation and methodology; Flowcharts; Impurities; Lithography; Logic devices; Passivation;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982658

Filename

982658