A high speed microprocessor core for the embedded applications-PKURS001

PKURS001, compatible with ARM7TDMI´s instructions and interface, is created in HLD (High Level Design) and verified in the class library of SYNOPSYS to reach more than 60 MHz. In this paper, we discuss some methods adopted in architecture design and data path design of PKURS001 to shorten its critical path and achieve such a high frequency. We push fetch on source operands, originally in the Instruction Execution stage, back to the Instruction Decoding stage. By this means, the critical path delay is decreased significantly with a balancing combinatorial path between the two stages. ALU is optimized to be more regular, to occupy less area and to reduce power consumption by sharing the same p and g function for both the arithmetic operation and the logical one. On the other hand, a leading zero anticipation algorithm, suitable for floating-point arithmetic, is changed and used in PKURS001´s Zero flag generation. This further decreases the critical path delay by making the flag generation and add or sub operation in parallel with little extra area cost