DocumentCode
2228745
Title
DRR A Fast High-Throughput Scheduling Algorithm for Combined Input Crosspoint-Queued CICQ Switches
Author
Luo, Junzhou ; Lee, Yong ; Wu, Jun
Author_Institution
Dept. of Comput. Sci. & Eng., Southeast Univ., Nanjing
fYear
2005
fDate
29-29 Sept. 2005
Firstpage
329
Lastpage
332
Abstract
With the continuing increase in density of VLSI, limited buffer can be placed inside the crossbar and this combined input-crosspoint-queued (CICQ) switch structure decouples the inputs and outputs matching. In this paper, an analysis of the performance of Round-Robin scheduling algorithm for CICQ switch has been made proves that the Round-Robin algorithm can achieve 100% throughput under uniform traffic but not stable under non-uniform traffic. We propose the DRR algorithm, which can achieve 100% throughput under arbitrary traffic even buffered only one cell in crosspoints in CICQ switch DRR algorithm is feasible for fast hardware implementation and its time complexity is O(1)
Keywords
VLSI; buffer storage; computational complexity; electronic switching systems; queueing theory; scheduling; telecommunication traffic; CICQ; DRR algorithm; Round-Robin scheduling algorithm; VLSI; buffer storage; combined input-crosspoint-queued switch; telecommunication traffic; very large scale integration; Algorithm design and analysis; Impedance matching; Packet switching; Performance analysis; Round robin; Scheduling algorithm; Switches; Throughput; Traffic control; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 2005. 13th IEEE International Symposium on
Conference_Location
Atlanta, GA
ISSN
1526-7539
Print_ISBN
0-7695-2458-3
Type
conf
DOI
10.1109/MASCOTS.2005.28
Filename
1521150
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