• DocumentCode
    2228864
  • Title

    High Performance Autoassociative Neural Network Using Network on Chip

  • Author

    Dong, Yiping ; Lin, Zhen ; Watanabe, Takahiro

  • Author_Institution
    Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan
  • fYear
    2009
  • fDate
    26-28 Dec. 2009
  • Firstpage
    4015
  • Lastpage
    4018
  • Abstract
    In this paper, an Artificial Autoassociative Neural Network (AANN) is implemented by Network on Chip (NoC) architecture to solve communication and performance problem. This proposed NoC based system can map four neurons in one PE and the whole system consists of PEs each of which connects with a router. This system is reconfigurable and extendable so that it can easily suit for different applications. Simulation results show that the proposed implementation method can reduce communication load and total computation time.
  • Keywords
    network routing; network-on-chip; neural nets; performance evaluation; PE; artificial autoassociative neural network; communication load reduction; computation time reduction; network on chip architecture; neurons mapping; processing element; router; Artificial neural networks; Computational modeling; Hardware; Information science; Network-on-a-chip; Neural networks; Neurons; Noise reduction; Production systems; Transfer functions;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Information Science and Engineering (ICISE), 2009 1st International Conference on
  • Conference_Location
    Nanjing
  • Print_ISBN
    978-1-4244-4909-5
  • Type

    conf

  • DOI
    10.1109/ICISE.2009.633
  • Filename
    5455373