Performance of compensation algorithms for direct-conversion receivers under finite wordlength constraints

Direct-conversion receivers have attracted increased attention recently as they represent an interesting architecture in portable wireless environments, where power, cost, and size are critical design constraints. They suffer, however, from various front-end impairments, with I/Q imbalance, DC offset, and flicker noise being among the most serious ones. Digital compensation algorithms have been proposed in the literature to cope with the adverse effects. Usually, these algorithms are analyzed by computer simulations in nearly infinitely precise arithmetic. A fixed-point finite wordlength implementation on DSPs, FPGAs, and ASICs typically results in a reduced performance. This paper investigates the performance degradation of various compensation algorithms due to a finite wordlength. The results obtained by bit-true simulations demonstrate that a moderate wordlength is sufficient to achieve results similar to infinite precision