Title :
1/4 W optical receiver and clock recovery circuit for Gb/s digital fiberoptic links
Author :
Daryoush, A.S. ; Zhang, X. ; Lin, J.Y.
Author_Institution :
Microwave Photonics Device Lab., Drexel Univ., Philadelphia, PA, USA
Abstract :
Design and simulation of a low power consuming MMIC chip set is presented in this paper, which is used as an optical receiver and clock recovery circuit operating up to 1.25 Gb/s. This design is based on BTA24 Si BJT transistor array from Bipolarics. Major design innovations such as push-pull self-oscillating mixer and a push-push frequency doubler is used to provide a total power consumption of 247 mW in an area of only 700 /spl mu/m/spl times/700 /spl mu/m.
Keywords :
bipolar MMIC; clocks; digital communication; integrated optoelectronics; optical fibre communication; optical receivers; 1.25 Gbit/s; 247 mW; 700 micron; BTA24 Si BJT transistor array; Bipolarics; Si; clock recovery circuit; design; digital fiber optic link; low power MMIC chip; optical receiver; push-pull self-oscillating mixer; push-push frequency doubler; simulation; Circuits; Clocks; Energy consumption; Frequency; Optical amplifiers; Optical design; Optical fiber devices; Optical fibers; Optical receivers; Optical transmitters;
Conference_Titel :
Microwave Symposium Digest, 1996., IEEE MTT-S International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3246-6
DOI :
10.1109/MWSYM.1996.511081
