CMOS analog neurofuzzy prototype based on ANFIS

Author

Arellano-Cardenas, O. ; Molina-Lozano, H. ; Moreno-Cadenas, J. ; Gomez-Castaneda, F. ; Flores-Nava, L.

Author_Institution

Electr. Eng. Dept., Inst. Politecnico Nacional, Mexico City, Mexico

Volume

3

fYear

2000

fDate

2000

Firstpage

726

Abstract

The architecture called ANFIS (Adaptive Neuro-Fuzzy Inference System) proposed by J.R. Jang (1993) is divided in five layers. Layers 1 and 2 in ANFIS were built by using a double-differential amplifier and a winner takes all circuit; to implement layers 3, 4 and 5, CMOS translinear blocks are used. The complete ANFIS architecture is implemented on a circuit board, using two CMOS circuits (N-well and 2 μm minimum dimensions). The total system has two inputs with three membership functions each one, which generate a fuzzy space with nine subspaces and one single output. The system is used for classification of electrical signals

Keywords

CMOS analogue integrated circuits; analogue processing circuits; fuzzy logic; neural chips; neural net architecture; signal classification; 2 micron; ANFIS architecture; CMOS analog neurofuzzy prototype; CMOS translinear blocks; WTA circuit; adaptive neuro-fuzzy inference system; double-differential amplifier; electrical signals classification; fuzzy space; membership functions; n-well CMOS process; winner takes all circuit; Circuits; Cities and towns; Differential amplifiers; Fuzzy logic; Fuzzy systems; Neural networks; Polynomials; Prototypes; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856163

Filename

856163