A VLSI low power solution for mobile satellite radio receivers

Two ICs have been implemented as part of a mobile digital satellite radio receiver. An RF front-end stage makes a superheterodyne frequency conversion from L band to 1.84 MHz IF, with a high level of integration, i.e only a SAW filter outside the chip. A fully digital channel decoder receives the IF signal from the RF front-end and converts it by means of an integrated 6-bit half flash A/D converter. Its main functions are a QPSK demodulator, a Viterbi decoder, a Reed-Solomon decoder, a deinterleaver and TDM extraction. The analogue input signal carrier is 1.84 MHz while the maximum chip frequency is about 10 MHz in order to optimize power consumption. Output data are transferred using a serial interface at a maximum rate of 128 kbit/s, The channel decoder is implemented using a five-metal layer CMOS 0.35 μm process, complexity is 1.5 million transistors, dissipating 50 mW with die size of 23 mm². For the RF front-end, implemented in a 20 GHz bipolar process, die size is 16 mm², power consumption is about 200 mW, and includes on-chip low noise amplifier, 3.6 GHz oscillator and two PLL loops