Design and Implementation of High-Performance Modular Exponentiation Arithmetic Unit

This paper describes the design and implementation of a high-performance modular exponentiation arithmetic unit based on Montgomery algorithm and FIPS method. We present an effective method of improving FIPS pipeline efficiency and optimizing the memory occupation. First, create multiple data paths to the multipliers input ports to use the units in multiplex; second, insert the zero value into the pipeline data sequence without generating additional memory space to store the temporary products; third, organize the inter-RAMs´ data sharing and iteration by FSM to keep smallest memory usage. It finally performs a high-speed and space-efficient modular exponentiation arithmetic unit. The design has been verified on Xilinx Virtex-5 FPGA platform with maximum frequency of 142MHz, only occupying eight 32×32 (1Kb) Dual-Prot Block RAMs totally. 1024-bit modular exponentiation can reach the speed of 123.15Kbps.