Characterizing standby leakage in high-performance flip-flops considering both subthreshold and gate leakage

This paper presents a state-dependent characterization of leakage power in selected high-performance flip-flops for 65 nm I V CMOS technology. The contributions of both the subthreshold and the gatecurrent were considered. Results show the dominance of the gate-leakage power as the main leakage mechanism as predictedfor the sub-100 nm regime.