DES-SRAM IP-core: a SRAM embedding DES feature [secure SoC applications]

This paper proposes a DES-SRAM IP-core dedicated to secure SoCs. This core is an optimized hardware implementation of a DES (data encryption standard) secret key algorithm. The main idea was to implement a DES feature inside a basic SRAM in order to suppress data transfers during data encryption and thus to avoid a bus bottleneck as well as to increase SoC security. The DES capability only adds few percent hardware overhead, and our modified SRAM offers two operating modes: a basic SRAM mode and an encryption mode. The DES-SRAM self-encrypts each 64 bit block of its own data in 17 clock cycles.